I am a 5th year Ph.D. student from the Department of Electrical Engineering at Princeton University, working with Prof. Sharad Malik. My research interest is to explore effective and efficient methods for modeling and verification of complex computing systems. Formal methods have been largely used in my research projects. My recent research project focuses on leveraging instruction-level hardware models in HW/SW co-simulation and hierarchical verification.

CV [Google Scholar] [GitHub] [LinkedIn]

Publications

Conferences

• Scaling SoC Verification through Instruction-Level Hardware Models

  Yue Xing, Huaixi Lu, Aarti Gupta, Sharad Malik 41st International Conference on Computer-Aided Design (ICCAD), 2022 [pdf]

• Generalizing Tandem Simulation: Connecting High-level and RTL Simulation Models

  Yue Xing, Aarti Gupta, Sharad Malik 27th Asia and South Pacific Design Automation Conference (ASP-DAC), 2022 [pdf]

• Leveraging Processor Modeling and Verification for General Hardware Modules

  Yue Xing, Huaixi Lu, Aarti Gupta, Sharad Malik
  Design, Automation and Test in Europe Conference (DATE), 2021 [pdf]
  Best Paper Award[Press]

• A Formal Instruction-Level GPU Model for Scalable Verification

  Yue Xing, Bo-Yuan Huang, Aarti Gupta, and Sharad Malik
  International Conference on Computer-Aided Design (ICCAD), 2018 [pdf]

• Approximate Adder with Hybrid Prediction and Error Compensation Technique

  Xinghua Yang, Yue Xing, Fei Qiao, Qi Wei, Huazhong Yang
  IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2016 [pdf]

Journals

• Multistage Latency Adders Architecture Employing Approximate Computing

  Xinghua Yang, Yue Xing, Fei Qiao, Huazhong Yang
  Journal of Circuits, Systems and Computers, 2017 [pdf]

Awards

• Princeton Graduate School Award for Excellence, Dec 2021[Press]
• Richard C. Hough Teaching Award, Sep 2021[Press]
• Best Paper Award (DATE), Feb 2021[Press]
• Princeton Ph.D. Fellowship, Sep 2016

Experience

Industrial

• Software Engineering Intern, Facebook. Jun 2020 - Aug 2020, Boston, MA, USA

  Interned in data infrastructure team.
  Researched on formal verification method in improving Facebook product service.
  Explored methods for query equivalence checking.

• Hardware Engineering Intern, Google. Jun 2018 - Dec 2018, Mountain View, CA, USA

  Implemented Quantization frameworkf for TensorFlow models.
  Developed, optimized end-to-end ML applications on domain specific accelerators.
  Measured and characterized performance and power for the accelerators.
  Explored a simulator-based power model for the accelerators.

Teaching

• Head Lab Instructor, ELE 206/COS 306 Contemporary Logic Design, Princeton University, Fall 2020
• Head Lab Instructor, ELE 206/COS 306 Contemporary Logic Design, Princeton University, Fall 2019
• Head Preceptor, ELE 206/COS 306 Contemporary Logic Design, Princeton University, Fall 2019
• Lab Instructor, ELE 206/COS 306 Contemporary Logic Design, Princeton University, Fall 2017
• Preceptor, ELE 206/COS 306 Contemporary Logic Design, Princeton University, Fall 2017

Mentoring

• Tinotenda Chinamora

  EE Department Undergrads Summer Internship Project, Summer 2020
  Advisor: Prof. Sharad Malik
  Project: Tandem Simulation between Instruction-level Abstraction (ILA) and RTL – Accelerator Case Studies

• Tinotenda Chinamora

  EE Department Undergrads Independent Project, Spring 2020
  Advisor: Prof. Sharad Malik
  Tandem Simulation between Instruction-level Abstraction (ILA) and RTL – Processor Case Studies